A Cathode Ray Tube (CRT) display generally provides the best brightness, highest contrast, best color quality and largest viewing angle of prior art computer displays. CRT displays typically use a layer of phosphor which is deposited on a thin glass faceplate. These CRTs generate a picture by using one to three electron beams which generate high energy electrons that are scanned across the phosphor in a raster pattern. The phosphor converts the electron energy into visible light so as to form the desired picture. However, prior art CRT displays are large and bulky due to the large vacuum envelopes that enclose the cathode and extend from the cathode to the faceplate of the display. Therefore, typically, other types of display technologies such as active matrix liquid crystal display, plasma display and electroluminescent display technologies have been used in the past to form flat panel displays.
Recently, a thin flat panel display commonly referred to as a field emission display (FED) has been developed which uses the same process for generating pictures as is used in CRT devices. These FEDs use a backplate including a matrix structure of rows and columns of electrodes. One such FED is described in U.S. Pat. No. 5,541,473 which is incorporated herein by reference. Typically, the backplate is formed by depositing a cathode structure (electron emitting) on a glass plate. The cathode structure includes emitters that generate electrons. The backplate typically has an active area surface within which the cathode structure is deposited. Typically, the active area surface does not cover the entire surface of the glass plate and a thin strip is left around the edges of the glass plate. The thin strip is referred to as a border or a border region. Conductive traces extend through the border to allow for electrical connectivity to the active area surface. These traces are typically covered by a dielectric film as they extend across the border so as to prevent shorting.
Prior art flat panel displays include a thin glass faceplate (anode) having a layer of phosphor deposited over the surface of the faceplate. A conductive layer is deposited on the glass or on the phosphor. The faceplate is typically separated from the backplate by about 1 millimeter. The faceplate includes an active area surface within which the layer of phosphor is deposited. The faceplate also includes a border region. The border is a thin strip that extends from the active area surface to the edges of the glass plate. The faceplate is attached to the backplate using a glass sealing structure. This sealing structure is typically formed by melting a glass frit in a high temperature heating step. This forms an enclosure which is pumped out so as to produce a vacuum between the active area surface of the backplate and the active area surface of the faceplate.
Prior art cathodic structures are typically formed by depositing a first layer of metal over a glass plate (first metal layer). This first metal layer is then masked and etched so as to form rows of conductive strips (row metal). Typically, a resistive layer formed of silicon carbide (SiC), cermet, or a combination of SiC and cermet is deposited over the row metal. A dielectric layer is then deposited. A second layer of metal is then deposited over the surface of the cathodic structure. A series of mask and etch steps are then performed so as to form a columns of conductive strips (column metal). The mask and etch steps also form openings in the column metal which extend through the dielectric layer so as to expose portions of the resistive layer. Emitters are formed over the exposed portions of the row metal and within the openings in the column metal by a series of deposition and etch steps. Individual regions of the cathode are selectively activated by applying electrical current to selected conductive strips of row metal and selected conductive strips of column metal so as to generate electrons which strike the phosphor so as to generate a display within the active area surface of the faceplate. These FEDs have all of the advantages of conventional CRTs but have the great advantage of being much thinner.
The first metal layer of a FED is typically formed of an alloy of nickel (approx. 92%) and vanadium (approx. 8%). A nickel vanadium alloy is used since it gives a good electrical bond with the overlying resistive layer and because it is resistant to damage and contamination in subsequent process steps. However, the resistivity of the nickel vanadium layer is approximately 55 micro-ohms-centimeter. This high resistivity causes signal delay. Signal delay causes decreased performance and inconsistent display quality. In addition, nickel vanadium alloy is expensive.
In an attempt to overcome the problems associated with the use of nickel vanadium alloy in row metal formation, manufacturers have attempted to use less resistive materials such as aluminum. However, many of these less resistive materials unfortunately do not meet process compatibility requirements. In addition, many of these less resistive materials typically do not form a sufficient electrical contact with the overlying resistive layer to function effectively. This is primarily due to the native oxide that forms on the surface of the conductive layer inhibiting current flow. In addition, subsequent process steps damage and contaminate the surface of the aluminum. In particular, the alkaline and acidic solutions used in subsequent process steps attacks aluminum. Moreover, subsequent rinsing and cleaning steps may leave deposits which adhere to the surface of the aluminum. These contaminants further degrade the quality of electrical contact between the row metal and the resistor.
One of the reasons that aluminum forms a poor electrical bond with the overlying resistive layer is oxidation of the surface of the aluminum. This oxidation results from exposure to atmospheric conditions. Prior art methods have attempted to get a good electrical bond between the Aluminum and the overlying resistive layer by performing an etch on the aluminum layer such as a sputter etch. This sputter etch removes accumulated oxidation (aluminum oxide). Though sputter etching gives good results for small surface areas, sputter etching does not give consistent coverage across the large surface areas required for current FEDs. For the above reasons, aluminum has significant disadvantages when used in forming row metal in prior art FED devices.
Accordingly, what is needed is a FED with row metal which minimizes signal delay and which meets signal propagation and other performance criteria and process compatibility criteria. In addition, a FED is needed which has row metal which is easy to deposit and etch and which can be formed using current processing techniques. Moreover, processing methods for forming a FED with row metal which has low resistivity and which forms a good bond with a resistive layer are required. Furthermore, processing methods are needed for forming a FED with row metal which is resistant to damage during subsequent processing steps. The present invention meets the above needs.